Mixed-Signal Modeling with Vanilla VHDL and Verilog
Steve Watkins and Kam Wong, Blue Pacific Computing
Abstract:
This paper compares and contrasts mixed-signal modeling using hardware description languages with and without the analog and mixed-signal extensions. We argue that there are several major advantages to performing mixed-signal modeling using VHDL and Verilog without the AMS extensions. We refer to this style of modeling as vanilla HDL mixed-signal modeling. Examples of vanilla mixed-signal codec models for both VHDL and Verilog are presented.
Introduction
Designers have been fighting the problem of modeling analog and digital mixed-signal systems for years. As we are entering into the system-on-chip (SOC) integrated circuits era, the problem has become more difficult due to the larger number of transistors [1,2]. The latest weapons in this fight are the analog and mixed-signal (AMS) extensions to the VHDL and Verilog* hardware description languages (HDL's). However, these AMS extensions bring some problems with them, which prompted us to ask: "How well can mixed-signal modeling be performed without the AMS extensions?" The answer is: "Well enough to make this our preferred methodology."
Some History
In the past, designers have used a variety of simulation methodologies to verify designs that contained both analog and digital circuits. At the very highest levels of abstraction, system designers have used C/C++ and Matlab* to model systems that would be implemented with analog and digital circuits; but this approach usually doesn't try to represent any implementation issues. At the next level down in the hierarchy, designers have used Saber* by Analogy and similar tools to model mixed-signal systems. At the lowest level of abstraction, designers have modeled all the analog and digital circuits at the transistor level and used Spice-like simulators, or reduced-complexity transistor-level simulators.
Designers are just beginning to use the VHDL and Verilog AMS languages, and this approach fits somewhere in the middle compared to the above levels. The AMS extensions allow a designer to use VHDL or Verilog to describe analog circuits at different levels of abstraction, ranging from behavioral to structural. The AMS description is usually then translated to a netlist and simulated with a Spice-like simulator.
Another approach offered by major CAD companies is to provide a simulation environment that allows the user to choose from different levels of abstraction for a given simulation. Digital blocks are represented with an HDL and simulated with an HDL simulator, analog blocks are represented with transistors or an AMS HDL and simulated with a Spice-like simulator. A software backplane allows the HDL and Spice simulators to communicate via interprocess communication.
Typically lower levels of abstraction translate to slower simulation time. Consequently, simulating large mixed-signal designs solely at the transistor level with a standard Spice-like simulator may not be practical. The benefits of Spice simulation tools are that they provide the most detailed level of modeling and analysis including: DC, transient, small signal AC, filters (LaPlace and zero/pole). The costs of Spice simulation are often long simulation times and tedious design entry.
The Benefits of AMS HDL Mixed-Signal Modeling
The analog and mixed-signal (AMS) extensions for VHDL and Verilog offer a new approach to mixed-signal modeling and simulation [3,4]. They extend the syntax and the semantics of vanilla VHDL and Verilog to allow these HDL’s to describe any type of analog behavior (including mechanical systems). See the Verilog AMS example of a digital-to-analog converter at the end of this paper.
The AMS extensions provide the means to perform behavioral mixed-signal modeling as compared to transistor-level Spice modeling, and this allows circuits to be represented at a higher level of abstraction [5]. The consequences of AMS behavioral modeling are faster simulation times and faster creation of the system earlier in the design cycle. And since AMS HDL models are usually simulated with Spice-like simulators, all of the traditional Spice type analyses and modeling options are also available.
Other benefits of the AMS extensions are: a technology-independent representation of the analog circuits, easier exploration of tradeoffs for different analog architectures, the creation of golden simulation results which can be used for regression comparison, circuits can be modeled as ideal or non ideal with specific non linearities, support of design reuse at the flexible behavioral level [6], and support of analog circuit intellectual property (IP) by not disclosing transistor-level circuit tricks.
The Benefits of Vanilla HDL Mixed-Signal Modeling
Analog and mixed-signal circuits can also be modeled with standard VHDL and Verilog. We'll refer to this style of modeling as vanilla HDL mixed-signal modeling. This type of modeling is usually at a higher level of abstraction than AMS HDL mixed-signal modeling. The key idea is to use the standard arithmetic operators (primarily multiplication and addition), and to use standard conversion functions to map between real numbers representing voltages in the analog domain and vectors representing logic values in the digital domain. Many SOC chips need only analog-to-digital converters (A2D) and/or digital-to-analog converters (D2A), and these are extremely easy to model using vanilla VHDL and Verilog techniques.
When coding with vanilla VHDL, real numbers are used on ports to represent analog inputs and outputs; CONV_INTEGER, CONV_STD_LOGIC_VECTOR, and type casting are used for conversion functions. For Verilog, 64-bit ports are used to represent analog input and output voltages; $realtobits and $bitstoreal and simple assignments are used for conversion functions.
There are several advantages of vanilla HDL mixed-signal modeling over AMS HDL modeling. The most important advantages are:
The vanilla approach is faster because simple arithmetic is used to compute the analog transient simulation results, while the AMS approach requires the Spice solution of ordinary differential equations via several complex steps [8]. We have found the vanilla approach to provide a speedup in simulation time by factors ranging from 10x to 50x. For example, we simulated a 4-bit D2A converter with three different models: transistor-level Spice schematic (with 50 transistors), Verilog AMS and vanilla Verilog. The simulations times for 1 microsecond of circuit simulation were: transistor-level 3.5 seconds; Verilog AMS 3.0 seconds; vanilla Verilog 0.1 second.
The vanilla models are portable to all industry standard HDL simulators because they use only the standard HDL language, and several vanilla HDL simulators support mixed-signal behavioral simulation by providing analog waveform viewing options (Blue Pacific's BlueHDL, Modeltech and Aldec).
Other vanilla HDL modeling advantages are: no new syntax or semantics for experienced HDL designers to learn, no new simulation environments to be learned or purchased, and better GUI waveform display for a large number of signals at once. These same benefits will also apply to using C/C++ HDL's for vanilla HDL mixed-signal modeling, once they become standardized.
The vanilla HDL modeling approach also provides the same benefits as the AMS HDL modeling approach over transistor-level mixed signal modeling listed in the above section. The main disadvantages of vanilla HDL modeling compared to AMS HDL modeling are: it can't provide the Spice-like analyses (DC operating point, small signal AC), and filters are harder to model. However, Spice-like analyses have to be performed at the pure transistor level eventually anyway, and filters can still be modeled with the vanilla HDL’s using difference equations.
Real World Examples
We've modeled sigma delta codecs, ethernet transceivers, and standalone A2D's and D2A's using these vanilla HDL modeling techniques. Also included in these circuits are analog switches, amplifiers and level shifters. We are primarily an analog IP and consulting company and this approach has allowed us to provide our customers with models that they can integrate into their SOC simulations using standard VHDL and Verilog simulators.
Conclusion
The AMS extensions to VHDL and Verilog are a good idea, particularly for SOC design. But so far they have received limited use, partly because they are relatively new and partly because they require learning new syntax and semantics and the acquisition of new simulation tools. There already exists a small group dedicated to the concept of the AMS extensions to the HDL's, and we are also very interested in this approach. However, to reach a wider group of designers, this methodology is going to have to provide more widespread standard simulation environments, and it will have to win over engineers from the three main recalcitrant groups of potential users: 1) system designers, who typically don't like VHDL or Verilog and prefer Matlab and C/C++; 2) analog designers, who typically don't like languages and prefer pictures; 3) digital designers, who typically will have to learn: analog design principles, and at least one new set of HDL syntax and semantics.
For now, we think that vanilla HDL mixed-signal modeling has some significant advantages over AMS HDL mixed-signal modeling, primarily simulation speed and universal portability of models. We have used this approach to successfully provide IP models to SOC design houses and will continue to do so for the foreseeable future.
Codec Examples
Download the VHDL and Verilog codec examples from www.bluepc.com/download.html.
* Matlab is a registered trademark of the Mathworks
* Saber is a registered trademark of Analogy
* Verilog is a registered trademark of Cadence Design Systems
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