VHDL, Verilog and SystemC with Blue Pacific
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VHDL, Verilog, SystemC, Tcl/Tk and FPGA Classes by Blue Pacific
Blue Pacific Computing is an EDA company that specializes in training and HDL simulation tools. We focus on VHDL, Verilog, SystemC and FPGA training in the Linux, Unix and MS Windows environments. We provide low-cost VHDL, Verilog and SystemC simulation tools with links to ATE gear, consulting services and the following training classes. The classes combine morning lecture and afternoon labs, with an emphasis on the hands-on, real-world lab exercises. Class sizes are kept small in order to provide personal attention.
List and Description of Classes
Hardware Design for Software People
VHDL
Verilog
SystemC
Tcl/Tk
FPGA Design
Class Cost
Blue Pacific offers training classes for the VHDL, Verilog and SystemC hardware description languages (HDL's), Tcl/Tk and FPGA design. These classes are from one to five days in length, depending on the experience and requirements of the students.
The HDL classes use the design of a small digital signal processor in concert with hands-on simulation to expose the student to all the major issues associated with a real design. Classes also include free design software that has been used by more than 30,000 students worldwide.
Hardware Design for Software People
This class is two days in length. It is intended for people who are familiar with software and who are curious about modern integrated circuit design using the Hardware Description Languages (HDL's). It is an overview of the four HDL's (Verilog, VHDL, C/C++ and Matlab), and the four main hardware technologies (ASIC's, structured ASIC's, FPGA's and ASSP's/platforms).The target audience includes: managers, programmers, engineers and technicians. The class will also be beneficial for experienced digital designers who would like an introduction to another Hardware Description Language. Familiarity with a high-level programming language such as C or C++ is the only prerequisite.
VHDL for Engineers and Programmers
Topics covered in the VHDL class are: introduction to the BlueHDL tools, correct coding style for Synopsys-style synthesis, the levels of abstraction (behavioral, RTL and structural), hierarchy (including test benches), port types, data types, assignments, operators, control flow, combinational logic, sequential logic, state machines, memories, entity and architecture pairs, processes, signals, variables, configurations, libraries, packages, procedures, functions, file input and output and a comparison of VHDL, Verilog and SystemC.The short introduction class is one day long and is the first day of the three-day introduction class. It introduces the BlueHDL tools and presents enough information for a student to continue learning on his/her own. The introduction class is three days long and covers up through state machines. The advanced class is two days long and covers additional topics.
Verilog for Engineers and Programmers
Topics covered in the Verilog class are: introduction to the BlueHDL tools, correct coding style for Synopsys-style synthesis, the levels of abstraction (behavioral, RTL, structural), hierarchy (including test benches), port types, data types, assignments, operators, control flow, combinational logic, sequential logic, state machines, memories, modules, initial and always statements, wires, registers (reg), tasks, functions, file input and output and a comparison of VHDL, Verilog and SystemC.The short introduction class is one day long and is the first day of the three-day introduction class. It introduces the BlueHDL tools and presents enough information for a student to continue learning on his/her own. The introduction class is three days long and covers up through state machines. The advanced class is two days long and covers additional topics.
SystemC for Engineers and Programmers
Topics covered in the SystemC class are: introduction to the BlueHDL tools, correct coding style for Synopsys-style synthesis, the levels of abstraction (behavioral, RTL, structural), hierarchy (including test benches), port types, data types, assignments, operators, control flow, combinational logic, sequential logic, state machines, memories, modules, asynchronous functions, asynchronous and synchronous threads, libraries, file input and output and a comparison of VHDL, Verilog and SystemC.The short introduction class is one day long and is the first day of the three-day introduction class. It introduces the BlueHDL tools and presents enough information for a student to continue learning on his/her own. The introduction class is three days long and covers up through state machines.
Tcl/Tk for Engineers and Programmers
The Tcl/Tk class is three days in length, and it assumes the student has experience with some programming language. The Tcl scripting language and the Tk toolkit create an ideal environment for developing a graphical user interface (GUI) that can run under all the major operating systems: MS Windows, Unix, Linux and the Macintosh OS. It is becoming an important aspect of EDA tool use and development. Topics covered are: the language basics, syntax, built-in procedures, user-defined procedures, the standard widgets, object-oriented features, using Tcl/Tk with C/C++, debugging and avoiding common mistakes.
FPGA Design
The FPGA design class is from three to four days in length, and is intended for both hardware and software people. Familiarity with a high-level programming language such as C or C++ is the only prerequisite. The emphasis is on using Hardware Description Languages to implement designs in FPGA's, and the students may use either VHDL or Verilog. The hands-on labs use the Digilent S3 FPGA Board with a Xilinx Spartan 3 FPGA. The class lectures cover both Xilinx and Altera FPGA technology. Topics covered include: FPGA architecture, FPGA design concepts, FPGA design tools, comparision of Xilinx and Altera families, development systems, PC to FPGA communication and implementation of embedded processors such as the Xilinx MicroBlaze 32-bit RISC CPU.