Bluepap: VHDL Simulation and Verilog Simulation with Blue Pacific. VHDL and Verilog for training and simulation.

VHDL and Verilog with Blue Pacific

VHDL and Verilog Simulation with BlueHDL

Abstract- This paper describes the BlueHDL hardware description language simulation tools from Blue Pacific Computing. These tools consist of: BlueVHDL, BlueVeri, BlueSim and BlueWave. BlueVHDL and BlueVeri are VHDL and Verilog compilers; BlueSim is a VHDL/Verilog digital simulator; BlueWave is a a graphical user interface (GUI) for controlling simulation and viewing simulation results. The tools are targeted for electrical and computer engineering students and for engineers performing module-level design. They run under both Linux and the MS Windows operating systems, and they have many features that can help better prepare students for hardware design, including analog/digital mixed-signal simulation and test vector generation for VLSI automatic test equipment.

Introduction

Both undergraduate and graduate electrical and computer engineering students need to be better trained before moving into industry. The gap is still too large between the education students receive and what the computer and telecommunications industries would like to see in a fresh graduate [1]. However, this is not an easy problem to solve. University faculty and administrators are aware of the problem, and they do their best to correct the situation. Engineering and computer science programs do evolve as the computer and telecommunications industries evolve, but still industry can never quite get what it would like (maybe this is not completely bad!).

A major deficiency in the education of electrical and computer engineering students is the lack of an inexpensive, modern design tool (primarily a digital simulator) that a student can own and use on his/her personal computer at home. For digital design and simulation, students need a simulator that is the equivalent of the inexpensive, Windows-based C/C++ compilers that are commercially available for software development. Nearly all computer science students own their development environments and use them on their home computers. Electrical and computer engineering students deserve this too. There is no comparison between the skills a student can develop when he/she can only use tools for a limited time in a computer lab versus the skills he/she can develop with unlimited access at home.

In order to redress this education deficiency, we have created a VHDL/Verilog digital simulator tool suite for students called BlueHDL. It consists of: two language compilers BlueVHDL and BlueVeri, a simulator BlueSim and a GUI results viewer called BlueWave. These tools are PC-based and are priced to fit a student's budget.

The initial simulator engine is event-driven and can simulate both VHDL and Verilog code. The BlueWave GUI results viewer also supports behavioral analog/digital mixed-signal simulation and test vector generation for VLSI automatic test equipment (ATE). The tools run under both Linux and MS Windows. They contain enough professional features to make them suitable for both education purposes and for performing module-level design.

Some Skills that Students Need and Our Solution

Electrical and computer engineering students need to learn several aspects of design related to simulation. These are: the VHDL and Verilog hardware description languages themselves; basic simulation tool use (run a simulation, display waves and tabular results, zoom in/out, etc.); the concepts of different types of simulation (behavioral, gate-level, post-layout, cycle-based, event-driven, analog/digital mixed-signal, hardware/software co-simulation); test vector generation for VLSI automatic test equipment (ATE).

It is easy to specify all the features in the world that instructors and students would like in a simulator, but is it feasible to actually create a low-cost simulator with all the features mentioned above? It is if the following ideas are followed: employ a small, but experienced development team; develop and release a limited beta version first, then add more features over time; keep the analog/digital mixed-signal and hardware/software co-simulation approaches very simple. We are not trying to compete with the best offerings of the commercial design automation companies, we are only trying to provide a tool with some commercial-level features that students can use to learn about these concepts. More details on this approach are presented later in the paper.

What About Existing Simulators?

The problem of not having an adequate student simulator arose to our attention as we prepared to teach a VHDL class at UCSD. We tested many VHDL simulators, but could find none that were at the same time: inexpensive, general and relatively powerful. In the first quarter of the class we used an inexpensive simulator from a programmable logic company and also a free demo version of a more expensive simulator. The programmable logic company's simulator was not general enough; it forced the students to synthesize everything to the gate-level, which meant no behavioral simulation, including no test benches. The free demo simulator was not bad, but it allowed simulation of only three small modules, which was not really powerful enough to teach a class. The second quarter we convinced UCSD to purchase a commercial tool at their generous academic discount. This simulator is industrial-strength and an excellent tool, but students cannot afford to purchase their own copy to use at home.

BlueHDL Features

The BlueHDL tool suite is targeted for a user community of EE/CS students and engineers doing module design. Both of these groups have similar HDL tool requirements; that is, they require a tool set that supports simulation with a limited number of source code modules but that has commericial quaility features. BlueHDL meets this requirement in that it has enough power to teach hardware description languages and simulation concepts, but not enough to do chip-level design (possibly hundreds of modules and a million or more nets).

Limiting the user community and the power of the simulator keeps it inexpensive, allowing any student to own a copy. The limited number of modules reduces the complexity of the software development and targeting only students instead of the commercial market allows us to limit both development and support costs.

The tool suite features VHDL and Verilog digital simulation, support of behavioral mixed-signal simulation with display of both digital and analog waveforms and tabular output views and both a graphical and command line user interface. Both VHDL and Verilog are supported because both are widely used [2], and future HDL's will most likely grow out of these existing languages [3].

Mixed-Signal and ATE Features

We have also developed mixed-signal and ATE utilities that allow generation of Hspice* and Pspice* vectors for analog simulation, and ATE test vector generation. While most students will not use ATE equipment with a project, the generation of ATE vectors allows the students to understand the concepts of test vectors; that is, forcing/sensing data, I/O masks and output strobe masks. The generation of spice analog simulation vectors is explained in the following section.

A Simple Approach to Digital/Analog Mixed-Signal Simulation

Many people believe that in the future integrated circuit design will be increasingly dominated by a system-on-chip (SOC) approach, which integrates both digital and analog blocks to create chips with millions of transistors. A consequence of this trend is that the creation and use of SOC CAD tools will be one of the main future challenges for VLSI design [4]. Many also believe that this challenge is already here. The BlueHDL tools give students an opportunity to understand and meet this challenge by providing a design tool for them with analog/digital mixed-signal simulation capability.

Our approach to digital/analog mixed-signal simulation is simple: we haven't tried to create a dynamic simulator with a backplane and complex interaction; instead, we have created a simple static simulation environment. BlueHDL utilities write and read snapshots in the form of vectors that interact with commercially available spice simulators. Both Hspice* and Pspice* analog simulators support this approach to mixed-signal simulation.

For the digital-to-analog simulation direction, the utilities generate files that these spice simulators can read which provide stimulus for their file-based D/A elements. For the analog-to-digital direction the spice simulators have A/D elements that can create digital output files, and the information in these files can be merged with existing test bench vector files. The mixed-signal simulation cycle is:

Run a digital simulation using estimated initial values for the inputs coming from the analog circuit.
Capture the results of the digital simulation required by the analog circuit in a vector file format that the analog simulator can read.
Run a spice analog simulation using the vector file as stimulus to the analog inputs.
Capture the results of the analog simulation and merge these results with an existing digital stimulus file readable by the digital testbench.
Repeat steps 1 through 4 (but now use captured analog input values instead of estimated ones).

This approach works best for simple analog/digital interfaces and will not work well for complex analog/digital interfaces with continuously changing interaction. We have tested this approach with both Hspice* and Pspice* for several different A/D converter architectures and active-pixel sensing circuits, and it works quite well.

The Future Features of the Simulator

Two additional major features are planned for a future version of the simulator, BlueSim: cycle-based simulation and hardware/software co-simulation with C/C++. For hardware/software co-simulation we are taking a similar approach to the analog/digital mixed-signal simulation: simulate only the interface and don't try to simulate all the software and hardware at the same time. Due to the limited performance of current personal computers it is not practical to do more. Since the simulator already has a C/C++ compiler (in order to create the executable code from the HDL source code), it is not a large addition to use C code as another form of source code for co-simulation.

Keeping the Cost Affordable

As mentioned above, a major design goal was to keep the simulator inexpensive (under one hundred dollars). The main way to do this was to limit its user community by targeting educational use and module design tasks. While theoretically there should not be much difference between a student simulator and a chip-level commercial simulator, there are two key differences: our user community requires only PC-based hardware and they do not demand a large sales and application support organization.

Developing for PC's allows the use of low cost development tools and hardware, while still giving the user a choice of operating systems: either Linux or MS Windows. Targeting a less demanding user group means that we can use the Web as the primary means of technical support, rather than an expensive hotline. The Web can be used to make the latest documentation available such as user's manual and tutorials, and also to provide a downloadable demo version. These factors mean we have been able to create, distribute and support the BlueHDL tools for a very low cost. The end result is that students can afford their own copy to use on their own PC.

Will Simulation Still Be a Necessary Skill in the Future?

One question to ask regarding CAD tools for students is: does the tool teach a skill that will serve the student in the long term? With formal verification coming into its own it makes sense to ask if digital simulation is really a skill that students will need to know in the future. We believe that simulation will never go away completely. While formal verification is maturing and reducing the need to simulate large numbers of vectors, even the formal verification community admits to the need for simulation [5]. Simulation will still continue to be used as the cornerstone of hardware design. It is the main tool that most engineers use to create, understand and functionally verify their designs.

Implementation Details

BlueSim is a language neutral, object-oriented and compiled-code digital simulator [6]. It can be used for behavioral system, register-transfer-level and structural gate-level simulation for various systems, boards and VLSI integrated circuit designs. Major features include a true bilingual and synthesis subset front-end parser [7], a multi-kernel simulation core and the employment of special optimization techniques for fast event-driven simulation speed [8].

The tool suite consists of three distinct programs: language compilers, a simulation kernel and a graphical user interface (GUI). The separation of the GUI and using Tcl/Tk as the GUI programming langauge has allowed BlueHDL to be easily ported to multiple operating systems. Currently this means Linux and MS Windows, but it could also easily be ported to other flavors of Unix (and run on work stations) in the future.

Bilingual and Synthesis Subset Front-end Parser

The BlueHDL language compilers feature a bilingual front-end with a parser that understands the pseudo Backus-Naur Form (BNF) of both VHDL and Verilog (as defined in the VHDL 1076-1993 Language Reference Manual (LRM) and the Verilog 1364-1995 Manual). Left-recursive rules defined in the languages have been removed to fit the LL(k) parser generator used in the front-end.

Most of mixed VHDL and Verilog simulators on the market require users to compile VHDL and Verilog files separately. BlueHDL allows users to mix and match VHDL and Verilog code during compilation and simulation using the patent-pending "Bilingual Parsing Technique". The parser reads the source code in either VHDL or Verilog and makes different decisions to build the abstract syntax tree (AST). As long as the interfaces between VHDL entities and Verilog modules are well defined, the code will be treated as if it has been written in only one language.

Another feature of this parser is the ability to flag non-synthesizable constructs. Commonly known non-synthesizable language constructs (such as "configuration" in VHDL and "fork" in Verilog) are parsed and tagged in the AST and warnings will be issued.

A true multilingual parser will be implemented in future releases of BlueHDL that will take native C code in addition to VHDL and Verilog. This will allow hardware and software co-simulation. As long as the "clock" concept is injected into the high-level C blocks, the interfaces between VHDL, Verilog and C modules can be established automatically by signal matching.

Conclusion

In order to help better prepare engineering and computer science students to lead the VLSI design industry into the next millenium, we have created a hardware description language simulation tool suite called BlueHDL. These tool suite was created with the concept in mind that students and working engineers should be able to use CAD tools at home on personal computers allowing unlimited time for development of design skills. The BlueHDL tools support the learning of hardware description languages and other important tasks such as mixed-signal simulation and issues related to commercial chip production with automatic test equipment.

* Hspice and Pspice are registered trademarks of their respective companies, Avant! and OrCad.

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