About: VHDL Training, Verilog Training and SystemC Training with Blue Pacific.

VHDL, Verilog and SystemC with Blue Pacific

VHDL, Verilog and SystemC Training and Simulation Tools with Blue Pacific

Blue Pacific Computing is an EDA company that specializes in HDL training and simulation tools. We provide free VHDL, Verilog and SystemC simulation tools for students.

For the past ten years we have also specialized in teaching the VHDL and Verilog hardware description languages for UCSD and for companies such as Synopsys, Cadence, Hewlett-Packard, Intel, Lockheed Martin, Rockwell, Alcatel, Nortel, Mitel, Nokia, Philips, ARM and many others.

Our BlueHDL and BlueWave tools run under Linux, Sun Sparc Solaris and MS Windows.

BlueHDL VHDL consists of a VHDL compiler, a simulation engine and the BlueWave GUI. BlueWave also doubles as a VCD results viewer that can be used with other commercial simulators such as Mentor Graphics* ModelSim VHDL and Verilog, Cadence* Verilog XL and NC Verilog and Open SystemC.

Linux, MS Windows, VHDL, Verilog and SystemC

Electronic system design currently is performed in the Unix, Linux and MS Windows environments using VHDL, Verilog and now C/C++ HDL's. We can provide the necessary experience and training to support this design activity. Our long-term vision is that:

Use of PC-based versions of Unix such as Linux will grow.
Use of MS Windows will grow in some areas of Design Automation.
The interaction between the Unix and Windows needs to improve.
VHDL and Verilog will continue to be the most widely used HDL's.
C/C++ HDL's such as SystemC will gain ground on VHDL and Verilog.
Blue Pacific can play a vital role in these areas.

Computer Education

Blue Pacific was founded in 1996 by two computer engineers with over thirty years of combined experience in VLSI design, programming, telecommunications and technical education. The company mission is to combine active consulting with teaching in order to provide our customers and students with state-of-the-art services and education. Our approach to teaching is based on a combination of lecture and hands-on programming experience, with an emphasis on the hands-on, real-world lab exercises. Our effectiveness in teaching the hardware description languages (HDL's) is increased by our experience in teaching and using a combination of VHDL, Verilog, SystemC and the C family of languages. The majority of our students wishing to learn one of the HDL's already have experience with the other HDL and/or C. With a few carefully chosen words, we can greatly increase a student's comprehesion of the unfamiliar HDL by pointing out the differences and similarities with the familiar HDL and/or C.

We bring a unique perspective to VLSI system design and computer education, drawing from our experience in the fields of digital and analog VLSI hardware design, and software development. We have worked on many ASIC projects and have implemented circuits and systems with the entire range of VLSI technologies, including standard cell, full custom and FPGA's from multiple sources. We also have many years of C/C++ programming experience. This combination of digital/analog hardware and C/C++ software experience allows us to bring a wide variety of viewpoints to design tasks and computer education. These viewpoints inform each other and help pave the way for true system-on-chip (SOC) design.

VHDL and Verilog Classes at UCSD, Synopsys and Elsewhere

For the past ten years we have been focusing on both VHDL and Verilog for digital hardware design, with an emphasis on synthesis with the Synopsys synthesis tools. For three years we taught a VHDL class at the University of California at San Diego, and for the past two years we have been teaching VHDL and Verilog at Synopsys and a variety of other companies including Hewlett-Packard, Intel, Lockheed Martin, Rockwell, Texas Instruments, Alcatel, Nortel, Mitel, Nokia and Philips (mostly through Esperan, which is now part of Cadence). In both our university and commercial classes our students have ranked our teaching as excellent (based on quantitative survey results).

Experience with EDA Tools from Synopsys, Cadence, Mentor and Others

We have extensive experience with both synthesis and simulation tools from all the major EDA vendors (Synopsys, Cadence, Mentor and Avanti). One of the founders, Kam Wong, has been certified in the Synopsys Ace program. We also have designed FPGA's and taught classes using tools from other vendors such as Xilinx, Altera and Orcad. We bring unbiased opinions to computer education regarding these commercial EDA tools and share our opinions freely.

Many Years of C/C++ Programming Experience

C and C++ are used extensively in the VLSI design world for hardware modeling and many other tasks. The founders have many years of experience programming with C and C++ for a variety of applications. We have created programs that range from simple translators to more complex programs such as operating systems for custom ATE systems, scan-based test tools and our BlueHDL simulation tools.

ASIC Consulting Services

Blue Pacific provides consulting services for VLSI design that include: FPGA design, design with VHDL, Verilog and SystemC, simulation, logic synthesis, synthesis links to layout, place and route, and test. These services are available on both a short-term and a long-term basis and can often be combined with training classes. Our consulting services expose us to the latest design methodologies and EDA tools, and this ensures our training classes are up to date.

The Founders and Principal Instructors

Steven S. Watkins

Steve received the degrees of B.S. in Physics and Philosophy from the California Institute of Technology, M.S. in Computer Science from UCSD, and Ph.D. in Electrical and Computer Engineering from UCSD. He has been involved with more than twenty VLSI chip design projects. He performed research in the the area of reduced-complexity analog and digital VLSI circuits for neural networks at UCSD and at the Caltech/NASA Jet Propulsion Laboratory, and has published more than a dozen conference and journal papers in areas ranging from VLSI design and test to neural networks and cellular telephone networks.

Steve has over twenty years experience in the computer, telecommunications and semiconductor industries designing VLSI circuits with schematic capture and hardware description languages (HDL's) and writing EDA programs with C, C++ and Tcl/Tk. Most recently he has been focusing on mixed-signal design and simulation with HDL's, and issues related to design reuse and HDL intellectual property. He has worked with Synopsys, Intel, IBM, Motorola, Bell Laboratories, Zilog, Rockwell Semiconductor, Hewlett-Packard, Alcatel, Texas Instruments, Lockheed Martin, Esperan, Silicon Connections, PCSI and Photobit. Steve has been creating and giving technical training classes his entire career.

Kameron H. Wong

Kam received the degrees of B.S. in Computer Engineering from UCSD, and M.S. in Electrical and Computer Engineering from UCSB. He has performed research in the the area of satellite communications at UCSB and has published several conference and journal papers. He is also certified in the Synopsys Ace Program.

Kam has over ten years experience in the computer, telecommunications and semiconductor industries designing VLSI circuits with hardware description languages and writing EDA programs with C and C++. He is an expert in the areas of logic synthesis and digital place and route. He has worked with Synopsys, Intel, Texas Instruments, Nokia, Nortel, Esperan, Metaflow, Spar, Silicon Connections, AMCC, PCSI, Proxima, Nuera Communications and Photobit. Kam has been involved with technical training throughout his career.

*Mentor Graphics ModelSim and Cadence are trademarks of their respective companies.